Marvell Expertise, Inc. a pacesetter in knowledge infrastructure semiconductor options, has expanded the packaging ecosystem for AI infrastructure with an modern multi-die resolution that lowers complete price of possession (TCO) for customized AI accelerator silicon. The superior packaging platform is a part of the Marvell™ complete IP portfolio for customized AI compute platforms—and permits multi-chip accelerator designs 2.8x bigger than typical single-die implementations. The Marvell method can allow extra environment friendly die-to-die interconnect, decrease energy consumption, elevated chiplet yields and decrease product price, and offers a producing various to conventional interposer-based multi-chip approaches. The packaging platform has been certified with a serious hyperscaler and is now ramping in manufacturing.
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Within the AI period, chip packaging has develop into vital for growing compute density whereas successfully managing energy, thermal dissipation, optical I/O, sign integrity, and different components that influence the efficiency and reliability in multi-die chiplet designs. Concurrently, rising provide chain complexity and prolonged lead instances current important challenges for scaling superior packaging options. The brand new Marvell packaging resolution permits hyperscalers to beat these boundaries, accelerating time-to-market whereas providing provide chain flexibility.
That is the newest innovation in a collection of developments for purchasers of Marvell customized XPU options. This extremely optimized multi-chip packaging platform was designed from the bottom up with the lately introduced Marvell customized HBM and CPO options in thoughts. Taken collectively, Marvell is constructing the trade’s broadest expertise platform to allow customized XPU design for the long run.
“Superior packaging is among the main autos for advancing compute density in AI clusters and cloud,” stated Will Chu, senior vp and normal supervisor of Customized Cloud Options at Marvell. “With out it, AI infrastructure can be considerably dearer and power-hungry. We sit up for collaborating with our companions and prospects to additional unlock the potential of superior packaging.”
“Chiplets represent one of the dynamic segments of the semiconductor market. We anticipate that chiplet processor income will develop by 31% per 12 months to succeed in $145 billion by 2030,” stated James Sanders, senior analyst at TechInsights. “Superior packaging applied sciences are vital to the evolution of chiplets, giving designers a framework through which to experiment.”
Interposers function the foundational layer with compute, dies, reminiscence, and different elements stacked above and speaking by means of the interposer. The Marvell re-distribution layer (RDL) affords a compelling various to conventional silicon interposers for knowledge heart purposes. The Marvell method integrates 1390 mm2 of silicon and 4 items of high-bandwidth reminiscence 3/3E (HBM3/3E) reminiscence stacks and makes use of six interposer RDL layers. This allows multi-die AI accelerator options which are 2.8 instances bigger than the biggest doable single-chip design. The Marvell multi-die packaging resolution permits for shorter die-to-die interconnects and a modular RDL interposer.
The Marvell RDL interposer reduces design price by means of its modular design. In typical chiplets, a single interposer will span the ground house of the chips it connects nicely as any space between them. If two computing cores are on reverse sides of a chiplet bundle, the interposer will cowl the whole house. Against this, Marvell RDL interposers are form-fitted to particular person computing dies and linked by high-bandwidth paths. Not solely does this method cut back supplies, it additionally will increase chiplet yields by enabling producers to switch particular person dies.
The Marvell multi-die packaging platform permits the mixing of passive gadgets to cut back potential sign noise throughout the chiplet bundle attributable to the facility provide. In collaboration with the packaging ecosystem, Marvell has prolonged the answer to assist a number of elements inside a single bundle, enabling the mixing of probably the most advanced AI designs.
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As well as, hyperscalers can now make use of the packaging expertise to construct XPUs with HBM3 and HBM3E reminiscence and Marvell is actively qualifying the expertise for future HBM4 designs.
Ecosystem Quotes
“Modern packaging applied sciences are vital to the adoption of chiplet architectures in present and future generations of AI and accelerated compute gadgets,” stated Dr. Mike Hung, senior vp at Superior Semiconductor Engineering (ASE). “Our shut collaboration with Marvell permits us to develop options that ship increased ranges of efficiency and effectivity, whereas reaching a broader viewers throughout the design ecosystem.”
“2.5D packaging expertise continues to modernize heterogeneous IC packaging, enabling high-performance, cost-effective integration of a number of chiplet and reminiscence modules,” stated Kevin Engel, chief working officer at Amkor Expertise. “This expertise not solely will increase I/O and circuit density, but in addition paves the way in which for superior 3D constructions, making it indispensable for the following era of purposes.”
“Probably the most sophisticated problem within the AI/ML resolution design is to create an efficient energy supply community, as GPUs are more and more utilizing extra energy. SEMCO is proud to have collaborated with Marvell to create a number one energy supply resolution utilizing its customized silicon capacitors and passive elements,” stated Taegon Lee, government vp and head of the Strategic Advertising and marketing Middle at Samsung Electro-Mechanics (SEMCO). “The ecosystem method we collectively took in creating this resolution will quickly develop into the norm. We sit up for continued collaboration with Marvell.”
“RDL-based chiplet integration provides Marvell the flexibleness to decide on the optimum course of expertise for every a part of their design,” stated CB Chang, president and CEO at Siliconware USA, Inc., a subsidiary of SPIL. “Because the trade continues to maneuver towards chiplet-based architectures, this flexibility permits extra advanced and environment friendly system integration.”
Marvell Customized Technique
The Marvell customized platform technique seeks to ship breakthrough outcomes by means of distinctive semiconductor designs and modern approaches. By combining experience in system and semiconductor design, superior course of manufacturing, and a complete portfolio of semiconductor platform options and IP—together with electrical and optical serializer/deserializers (SerDes), die-to-die interconnects for 2D and 3D gadgets, silicon photonics, co-packaged copper, customized HBM, system-on-chip (SoC) materials, optical IO, and compute cloth interfaces equivalent to PCIe Gen 7— Marvell is ready to create platforms in collaboration with prospects that remodel infrastructure efficiency, effectivity and worth.
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