Cadence introduced the tapeout of the {industry}’s first LPDDR6/5X reminiscence IP system answer optimized to function at 14.4Gbps, as much as 50% sooner than the earlier era of LPDDR DRAM. The brand new Cadence® LPDDR6/5X reminiscence IP system answer is a key enabler for scaling up the AI infrastructure to accommodate the reminiscence bandwidth and capability calls for of next-generation AI LLMs, agentic AI and different compute-heavy workloads for varied verticals. A number of engagements are at the moment underway with main AI, high-performance computing (HPC) and knowledge heart prospects.
The evolution of knowledge facilities from HPC compute virtualization to AI coaching and inference at scale has pushed a large buildout of AI infrastructure, and designing for environment friendly knowledge motion through reminiscence interfaces has by no means been extra essential.
The Cadence IP for the JEDEC LPDDR6/5X commonplace consists of a sophisticated PHY structure and a high-performance controller designed to maximise energy, efficiency and space (PPA) whereas supporting each LPDDR6 and LPDDR5X DRAM protocols for optimum flexibility. The answer helps native integration into conventional monolithic SoCs in addition to multi-die system architectures by leveraging the Cadence chiplet framework, enabling heterogeneous chiplet integration. The chiplet framework, together with the earlier LPDDR era, was efficiently taped out in 2024.
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“The evolution of knowledge facilities from HPC compute virtualization to AI coaching and inference at scale has pushed a large buildout of AI infrastructure, and designing for environment friendly knowledge motion through reminiscence interfaces has by no means been extra essential. LPDDR6 has emerged as a key enabler of accelerated compute, offering the velocity, bandwidth, energy profile and capability wanted to effectively carry out AI inference,” mentioned Boyd Phelps, senior vp and basic supervisor of the Silicon Options Group at Cadence. “With this tapeout, Cadence is continuous our monitor document of reminiscence IP management by providing an industry-first LPDDR6 implementation delivered as an built-in subsystem optimized for buyer functions.”
The entire PHY and controller reminiscence system boasts a brand new high-performance, scalable and adaptable structure primarily based on Cadence’s confirmed and extremely profitable DDR5 12.8Gbps, LPDDR5X 10.7Gbps and GDDR7-36G product traces. This primary providing in Cadence’s new LPDDR6 IP product line helps the LPDDR6 and LPDDR5X requirements, together with LPDDR5X CAMM2.
Appropriate for the AI, cellular, shopper, enterprise HPC and cloud knowledge heart markets, the superior LPDDR6/5X reminiscence IP system answer permits most flexibility for finish merchandise with a variety of efficiency, capability and value targets—guaranteeing lengthy manufacturing runs. The LPDDR6/5X PHY is customizable for various package deal and system topologies and accessible as a drop-in hardened macro. This ensures quick and dependable integration, translating into speedy time to market.
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The Cadence LPDDR6/5X controller features a full set of industry-standard and superior options for reminiscence interfaces, resembling assist for the Arm® AMBA® AXI bus. The reminiscence controller is offered as a smooth RTL macro for max flexibility in options, energy, space and efficiency.
The Cadence LPDDR6 answer contains the LPDDR6 Reminiscence Mannequin, which allows engineers to carry out complete verification and be certain that system-on-chip (SoC) designs are suitable with the newest JEDEC interface commonplace, accelerating their adoption of this new expertise with confidence. The LPDDR6 Reminiscence Mannequin features a full set of protocol checks, purposeful protection and a verification plan.
Obtainable now for buyer engagements, the brand new LPDDR6/5X IP is the newest addition to Cadence’s complete household of reminiscence IP system options, which additionally contains DDR, GDDR and HBM. Cadence Reminiscence IP is designed with the corporate’s industry-leading analog/mixed-signal design instruments. When mixed with Cadence’s UCIe™-based chiplet framework, the brand new LPDDR6/5X IP and Cadence’s different main reminiscence and interface IP ship an optimized answer that allows speedy chiplet realization.
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